Shubham Upadhyay
VLSI Design Engineer

Crafting High-Performance Silicon from RTL to Tapeout

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15+
RTL Projects
8
FPGA Designs
98%
Coverage

Featured Projects

Network-on-Chip router RTL to GDSII implementation

🧠 NoC Router RTL2GDSII

Implementation of a 2D-mesh Network-on-Chip router from RTL to GDSII using the OpenROAD flow and open-source PDKs.

2D
Mesh Topology
Wormhole
Switching
RTL→GDSII
Flow
OpenROAD
Backend
NoC RTL Design Physical Design OpenROAD
View on GitHub →
Round-robin arbiter waveforms

🔁 Round-Robin Arbiter

Fair round-robin bus arbiter with starvation-free scheduling and multi-testbench verification.

4
Masters
RR
Policy
No
Starvation
TB
Sanity+Stress
Verilog Arbiter Bus Verification
View on GitHub →
RISC-V 5-stage pipeline diagram

🧠 RISC-V RV32I Processor

RV32I core with both single-cycle and 5-stage pipelined implementations, including hazard detection and forwarding.

RV32I
ISA
5-stage
Pipeline
HD
Hazards
TB
Core-Level
RISC-V Verilog Pipelining CPU Design
View on GitHub →
Asynchronous FIFO with dual clock domains

⏱️ Asynchronous FIFO (Dual-Clock)

Dual-clock asynchronous FIFO with Gray-coded pointers, synchronizers, and focused CDC verification.

2
Clock Domains
Gray
Pointers
CDC
Safe
TB
Randomized
Verilog CDC FIFO Verification
View on GitHub →
Smart traffic controller state diagram

🚦 Smart Traffic Light Controller FSM

Sensor-driven traffic controller with emergency override, adaptive timing, and waveform-verified state coverage.

8
States
100%
FSM Cov
One-hot
Encoding
TB
Constrained
FSM Verilog Timing Control Logic
View on GitHub →
Synchronous FIFO block diagram

💾 Synchronous FIFO with Gray Code Pointers

Production-ready FIFO with Gray-code pointers, full/empty detection, and clean CDC boundaries for SoC datapaths.

Sync
Clocking
Gray
Pointers
Param
Depth/Width
TB
Self-Checking
Verilog SystemVerilog FIFO CDC
View on GitHub →
Dual-port SRAM architecture

🔲 Dual-Port SRAM with Collision Detection

True dual-port memory with configurable depth/width, read-during-write definition, and collision detection.

2
R/W Ports
Sync
Access
Flags
Collisions
RTL
Synth-Ready
Memory Verilog Dual-Port Verification
View on GitHub →
8x8 Dadda multiplier reduction tree

✖️ 8×8 Dadda Multiplier Analysis

Structural implementation of an 8×8 Dadda multiplier with delay and power analysis at 45 nm.

8×8
Operands
Tree
Reduction
45 nm
Node
SPICE
Analysis
Arithmetic Low Power SPICE Timing
View on GitHub →
Sorting algorithm visualization

📊 Sorting Algorithm Visualizer

Python-based GUI to visualize classic sorting algorithms and their time-step evolution.

5+
Algorithms
Step
By-Step View
Pause
Control
Live
Metrics
Python Algorithms Visualization
View on GitHub →
LFSR feedback taps diagram

🔐 Linear Feedback Shift Register (LFSR)

Parameterizable LFSR for pseudo-random sequence generation, suitable for DFT pattern generation and simple cryptographic primitives.

Param
Width
Taps
Configurable
PRBS
Sequence
TB
Coverage
Verilog DFT PRBS Digital Design
View on GitHub →

🛠️ Technical Skills

💻 Hardware Description Languages

Verilog SystemVerilog VHDL

🔧 RTL Design

FSM Design Datapath/Controller Pipelining CDC Low Power Arithmetic Units

✅ Verification

SystemVerilog Assertions UVM Coverage-Driven Formal Verification Waveform Debug

⚡ Synthesis & Timing

Synopsys DC Genus Yosys SDC Constraints STA CTS

📐 Physical Design

Floorplanning Placement Routing DRC/LVS OpenROAD IR Drop

🛠️ EDA Tools

Vivado Quartus ModelSim VCS Icarus GTKWave Verdi

🔍 Design for Test

Scan Insertion ATPG Boundary Scan BIST Fault Simulation

🤖 Scripting & Automation

Python TCL Perl Make Shell Git CI/CD

🔗 Bus Protocols

AMBA (AHB/APB) AXI Wishbone UART SPI I2C

🎛️ FPGA Platforms

Xilinx (Artix-7, Zynq) Intel (Cyclone, Arria) ChipScope/ILA FPGA Debug

Professional Experience

Graduate Teaching Assistant – EPICS

Purdue University | Indianapolis, IN | Aug 2024 – May 2025

  • Mentored 12+ student teams on engineering design projects with emphasis on RTL and embedded systems
  • Developed evaluation criteria for FPGA-based capstone projects
  • Conducted weekly design reviews covering specification, implementation, and verification phases

Engineering Intern – VLSI Design

Thyssenkrupp Crankshaft Company | Illinois, USA | May 2024 – Aug 2024

  • Designed parameterized RTL blocks for real-time measurement systems with <5ns latency requirements
  • Developed self-checking testbenches achieving 98% functional coverage using SystemVerilog assertions
  • Reduced integration time by 20% through modular design and comprehensive verification strategy
  • Synthesized designs targeting Xilinx Artix-7 achieving 150 MHz operation with 65% LUT utilization

Junior Electrical Manager

21 Knots Engineering | Mumbai, IN | Feb 2022 – Jul 2023

  • Coordinated electrical design and procurement for industrial automation projects
  • Led team of 5 engineers in power distribution and control systems implementation

Senior Electrical Design Engineer

Petrocil Engineering | Mumbai, IN | Jun 2019 – Jan 2022

  • Delivered detailed electrical designs and CAD drawings for oil & gas industry clients
  • Ensured compliance with international standards (IEC, IEEE) in all deliverables

🎓 Certifications

Selected coursework and industry training across computer architecture, RISC-V, Git, RTL design, and Cadence flows.

Computer Architecture Essentials certificate
Completed · LinkedIn Learning

Computer Architecture Essentials

Fundamentals of pipelines, memory hierarchy, and performance trade-offs in modern processors.
Computer Architecture
Getting Started with RISC-V certificate
Completed · LinkedIn Learning

Getting Started with RISC-V

RISC-V ISA basics, toolchain setup, and workflows for open instruction set architectures.
RISC-V
Git Essential Training certificate
Completed · LinkedIn Learning

Git Essential Training

Version control, branching, collaboration, and GitHub-based workflows for hardware projects.
Git / GitHub
Perl 5 Essential Training certificate
Completed · LinkedIn Learning

Learning PERL for EDA Scripting

Mastered Perl one-liners for efficient text processing, regex pattern matching, and command-line automation in scripting workflows.
Verilog · FPGA
Learning Verilog for FPGA Development certificate
Completed · LinkedIn Learning

Learning PERL for EDA Scripting

Verilog RTL development for FPGA applications.
Verilog · FPGA
Cadence RTL-to-GDSII Flow certificate
Completed · Cadence

Cadence RTL-to-GDSII Flow v7.0

End-to-end digital implementation flow: synthesis, place-and-route, timing closure, and signoff.
Physical Design Flow
Digital Design and Signoff certificate
Completed · Cadence

Digital Design and Signoff Academic Curriculum v1.0 (Online)

Digital implementation, timing analysis, power optimization, and signoff verification.
Digital Signoff
Static Timing Analysis-1 (VSD)
Completed · Udemy

Digital Design and Signoff Academic Curriculum v1.0 (Online)

Timing Path Analysis, Setup and Hold Time Verification, On-Chip Variation (OCV) Timing, Latch Timing Analysis, STA
Static Timing Analysis
Verilog HDL_VLSI Hardware Design Comprehensive Masterclass
Completed · Udemy

Verilog HDL_VLSI Hardware Design Comprehensive Masterclass

RTL Design (Verilog/VHDL), Application-Specific Integrated Circuits (ASIC), FPGA & ASIC Design Flow
Verilog · HDL

📬 Get In Touch

Open to opportunities in VLSI design, verification, and physical implementation. Let's connect!

✉️ vlsi.shubh@gmail.com 💻 github.com/VLSI-Shubh 🔗 linkedin.com/in/shubhamupadhyay0804
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