Shubham Upadhyay | Digital IC Design Engineer (RTL & FPGA/ASIC Design)

Featured Projects

Network-on-Chip router RTL to GDSII implementation

NoC Router RTL2GDSII

Implementation of a 2D-mesh Network-on-Chip router from RTL to GDSII using the OpenROAD flow and open-source PDKs.

Mesh Topology

Wormhole

Switching

RTL→GDSII

Flow

OpenROAD

Backend

NoC RTL Design Physical Design OpenROAD

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Round-Robin Arbiter

Fair round-robin bus arbiter with starvation-free scheduling and multi-testbench verification.

Masters

Policy

Starvation

Sanity+Stress

Verilog Arbiter Bus Verification

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RISC-V RV32I Processor

RV32I core with both single-cycle and 5-stage pipelined implementations, including hazard detection and forwarding.

RV32I

ISA

5-stage

Pipeline

Hazards

FWD

Forwarding

RISC-V Verilog Pipelining CPU Design

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Asynchronous FIFO with dual clock domains

Asynchronous FIFO (Dual-Clock)

Dual-clock asynchronous FIFO with Gray-coded pointers, synchronizers, and focused CDC verification.

Clock Domains

Gray

Pointers

CDC

Safe

Randomized

Verilog CDC FIFO Verification

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Smart Traffic Light Controller FSM

Sensor-driven traffic controller with emergency override, adaptive timing, and waveform-verified state coverage.

States

100%

FSM Cov

One-hot

Encoding

Constrained

FSM Verilog Timing Control Logic

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Synchronous FIFO with Gray Code Pointers

Production-ready FIFO with Gray-code pointers, full/empty detection, and clean CDC boundaries for SoC datapaths.

Sync

Clocking

Gray

Pointers

Param

Depth/Width

Self-Checking

Verilog SystemVerilog FIFO CDC

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Dual-Port SRAM with Collision Detection

True dual-port memory with configurable depth/width, read-during-write definition, and collision detection.

R/W Ports

Sync

Access

Flags

Collisions

RTL

Synth-Ready

Memory Verilog Dual-Port Verification

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8×8 Dadda Multiplier Analysis

Structural implementation of an 8×8 Dadda multiplier with delay and power analysis at 45 nm.

8×8

Operands

Tree

Reduction

45 nm

Node

SPICE

Analysis

Arithmetic Low Power SPICE Timing

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Linear Feedback Shift Register

Parameterizable LFSR for pseudo-random sequence generation, suitable for DFT pattern generation and simple cryptographic primitives.

Param

Width

Taps

Configurable

PRBS

Sequence

Coverage

Verilog DFT PRBS Digital Design

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ESP32 IoT edge-to-cloud system architecture

ESP32 Multi-Sensor IoT Edge-to-Cloud System

Firmware platform for ESP32-based multi-sensor telemetry with real-time acquisition, local buffering, MQTT-based cloud sync, and robust delivery under intermittent networks.

FreeRTOS

Firmware

MQTT

Transport

LittleFS

Persistence

OTA

Updates

C/C++ ESP32 FreeRTOS MQTT Docker Linux IoT

Sorting Algorithm Visualizer

Python-based GUI to visualize classic sorting algorithms and their time-step evolution.

Algorithms

Step

By-Step View

Pause

Control

Live

Metrics

Python Algorithms Visualization

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Featured Blog Posts

Technical insights on VLSI design, RTL, verification, and hardware engineering.

Synthesizable ≠ Efficient FPGA Implementation

Understanding why synthesizable RTL doesn't guarantee efficient FPGA implementation covering BRAM inference, resource optimization, and critical timing verification.

RTL FPGA BRAM Timing

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Understanding Synthesis: What Makes Verilog Code Synthesizable

A deep dive into Verilog synthesis fundamentals, exploring constructs, blocking vs non-blocking assignments, and why some code translates to hardware while others don't.

Synthesis RTL Verilog

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The RAM Shortage Crisis!

Exploring how AI's explosive growth is straining global RAM supply chains and reshaping memory architecture demands.

RAM HBM AI Memory

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HDLs Are NOT Programming Languages!

Demystifying the fundamental differences between Hardware Description Languages and Programming Languages, from syntax to execution models.

HDL Verilog Beginner

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Explore All Blog Posts

Dive deeper into my technical writing on RTL design, verification, FPGA implementation, synthesis, and hardware engineering topics.

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Technical Skills

Hardware Description Languages

Verilog SystemVerilog VHDL

RTL Design

FSM Design Datapath/Controller Pipelining CDC Low Power Arithmetic Units

Verification

SystemVerilog Assertions UVM Coverage-Driven Formal Verification Waveform Debug

Synthesis & Timing

Synopsys DC Genus Yosys SDC Constraints STA CTS

Physical Design

Floorplanning Placement Routing DRC/LVS OpenROAD IR Drop

EDA Tools

Vivado Quartus ModelSim VCS Icarus GTKWave Verdi

Design for Test

Scan Insertion ATPG Boundary Scan BIST Fault Simulation

Scripting & Automation

Python TCL Perl Make Shell Git CI/CD

Bus Protocols

AMBA (AHB/APB) AXI Wishbone UART SPI I2C

FPGA Platforms

Xilinx (Artix-7, Zynq) Intel (Cyclone, Arria) ChipScope/ILA FPGA Debug

Embedded Firmware

C/C++ Embedded C ESP32 Interrupts LittleFS

RTOS & Connectivity

FreeRTOS Wi-Fi Provisioning MQTT OTA HTTP/WebServer WebSockets

Sensors

1-Wire (DS18B20) MPU6050 BME280 DS18B20 DHT22 BMP280 BH1750 HC-SR04 INA219

Debugging & Deployment

GDB JTAG Serial Logging Docker MQTT Broker Linux

Professional Experience

Firmware/Hardware Engineer

WinWinLabs (Volunteer) | Remote | Aug 2025 – Present

Developed C/C++ firmware for ESP32 IoT devices supporting multi-sensor telemetry, MQTT communication, OTA updates, and local persistence under real-time constraints.
Tested and debugged embedded systems across fault conditions, validating interrupt-driven operation, network recovery, storage safety, and device-to-backend data integrity.

Graduate Teaching Assistant – EPICS

Purdue University | Indianapolis, IN | Aug 2024 – May 2025

Mentored 12+ student teams on engineering design projects with emphasis on RTL and embedded systems
Developed evaluation criteria for FPGA-based capstone projects
Conducted weekly design reviews covering specification, implementation, and verification phases

Engineering Intern

Thyssenkrupp Crankshaft Company | Illinois, USA | May 2024 – Aug 2024

Evaluated electrical compatibility and lifecycle status of Marposs inspection systems across multiple production machines, supporting upgrade planning and minimizing integration risks during phased modernization.
Created standardized electrical BOMs and documentation, working with OEM support teams to align replacement components and improve maintenance readiness.

Junior Electrical Manager

21 Knots Engineering | Mumbai, IN | Feb 2022 – Jul 2023

Coordinated electrical design and procurement for industrial automation projects
Led team of 5 engineers in power distribution and control systems implementation

Senior Electrical Design Engineer

Petrocil Engineering | Mumbai, IN | Jun 2019 – Jan 2022

Delivered detailed electrical designs and CAD drawings for oil & gas industry clients
Ensured compliance with international standards (IEC, IEEE) in all deliverables

Certifications

Selected coursework and industry training across computer architecture, RISC-V, Git, RTL design, and Cadence flows.

Completed · Cadence

Cadence RTL-to-GDSII Flow v7.0

End-to-end digital implementation flow: synthesis, place-and-route, timing closure, and signoff.

Physical Design Flow

Completed · Cadence

Digital Design and Signoff Academic Curriculum v1.0

Digital implementation, timing analysis, power optimization, and signoff verification.

Digital Signoff

Completed · Udemy

Static Timing Analysis - Part 1

Timing Path Analysis, Setup and Hold Time Verification, On-Chip Variation (OCV) Timing, Latch Timing Analysis, and STA fundamentals.

Static Timing Analysis

Verilog HDL_VLSI Hardware Design Comprehensive Masterclass

Completed · Udemy

Verilog HDL Hardware Design Comprehensive Masterclass

RTL Design (Verilog/VHDL), Application-Specific Integrated Circuits (ASIC), and FPGA & ASIC Design Flow.

Verilog · HDL

Completed · LinkedIn Learning

Computer Architecture Essentials

Fundamentals of pipelines, memory hierarchy, and performance trade-offs in modern processors.

Computer Architecture

Completed · LinkedIn Learning

Getting Started with RISC-V

RISC-V ISA basics, toolchain setup, and workflows for open instruction set architectures.

RISC-V

Completed · LinkedIn Learning

Git Essential Training

Version control, branching, collaboration, and GitHub-based workflows for hardware projects.

Git / GitHub

Completed · LinkedIn Learning

Learning Perl for EDA Scripting

Mastered Perl one-liners for efficient text processing, regex pattern matching, and command-line automation in scripting workflows.

Perl · Scripting

Completed · LinkedIn Learning

Learning Verilog for FPGA Development

Verilog RTL development for FPGA applications.

Verilog · FPGA

Get In Touch

Open to opportunities in VLSI design, verification, and physical implementation. Let's connect!

vlsi.shubh@gmail.com github.com/VLSI-Shubh linkedin.com/in/shubhamupadhyay0804

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