Blog
Thoughts on VLSI design, RTL, verification, and hardware engineering
Synthesizable ≠Efficient FPGA Implementation
Understanding why synthesizable RTL doesn't guarantee efficient FPGA implementation covering BRAM inference, resource optimization, and critical timing verification.
Read MoreUnderstanding Synthesis: What Makes Verilog Code Synthesizable
A deep dive into Verilog synthesis fundamentals, exploring constructs, blocking vs non-blocking assignments, and why some code translates to hardware while others don't.
Read MoreThe RAM Shortage Crisis!
Exploring how AI’s explosive growth is straining global RAM supply chains and reshaping memory architecture demands.
Read MoreHDLs Are NOT Programming Languages!
Demystifying a common misunderstanding among students entering VLSI. Learn the fundamental differences between Hardware Description Languages and Programming Languages, from syntax to execution models.
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